1. Field of the Invention
The present invention relates to a PLL (phase-locked loop) circuit and a phase control method of the PLL circuit, and more particularly to a PLL circuit having a phase build-out function of Stratum 3E clocks recommended by Telcordia GR-1244-CORE and a phase control method of the PLL circuit.
2. Background of the Related Art
The detailed specifications and functions of Stratum 3E clocks are recommended by Telcordia GR-1244-CORE. A phase build-out function is included in such functions. When a PLL circuit is designed according to the specifications in compliance with the Telcordia, two problems occur concerning restructuring of an output phase due to input phase noises.
First, since a transient wander generated within an interval time cannot be detected, restructuring of an output phase, which is to be essentially carried out, is not conducted. Second, when a cycle wander generated periodically is sometimes detected, wrong restructuring of the output phase is carried out. These two problems will be described in detail.
First, according to Telcordia GR-1244-CORE, the interval time of the phase build-out function is defined as 100 ms. Hence, as shown in FIG. 1, when a transient wander as an input phase noise is input, a maximum phase difference Y(ns) cannot be sometimes accurately detected. This is why the transient wander is inspected at that interval time and a momentary phase shift beyond twice the period (frequency of 5 Hz) of 100 ms cannot be detected. In order to detect a phase shift as momentarily as possible, one detecting method has proposed, as shown in FIG. 2. In FIG. 2, by changing interval time every sampling time, areas of up to a half frequency of the sampling time can be detected. However, when a transient wander synchronized with the interval time is generated, no detection can be occasionally performed.
Further, a cycle wander as an input phase noise is detected at the same time. As to the cycle wander, restructuring of the output phase should not be implemented. It is not easy that only the phase shift generated at the sampling time, as described above, is detected to determine either of the cycle wander and the transient wander.
In a conventional technique, as disclosed in Japanese Patent Application Laid-Open No. 2000-244472, a frame phase synchronous circuit for reducing an abrupt change of an output phase to a minimum is proposed. In this case, a plurality of sections for a phase difference between an input frame and an output frame are set and different voltages for controlling a VCO (voltage-controlled oscillator) depending on the phase difference are supplied. However, this device cannot solve the above-described two problems.